********************************************************************** ADVANCE PROGRAM & CALL FOR PARTICIPATION ********************************************************************** Workshop on Network Processors - NP2 http://www.cs.washington.edu/NP2/ Anaheim, California February 8-9, 2003 Held in conjunction with HPCA 9 - the 9th International Symposium on High-Performance Computer Architecture http://www.cs.arizona.edu/hpca9 February 8-12, 2003 NEWS * Advance registration deadline is 5:00 PM EST, Friday Jan 17 * NP2 has been extended to 1.5 days. HIGHLIGHTS The workshop will feature: * 13 original research papers * A keynote address by Jonathan Turner of Washington University in St. Louis * An invited talk by Ravinder Sabhikhi of IBM * A moderated industry panel session OVERVIEW Network processor design is an emerging field with challenges and opportunities both numerous and formidable. The goal of this workshop is to provide a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. ADVANCE PROGRAM SATURDAY, FEBRUARY 8 ******************** 1:25-1:30 - Opening Remarks 1:30-3:00 - Session 1: Hardware 1 A Programmable Scalable Platform for Next Generation Networking Christos J.Georgiou, Valentina Salapura, and Monty Denneau IBM T.J. Watson Research Center Power Considerations in Network Processor Design Mark A. Franklin and Tilman Wolf Washington University in St. Louis, University of Massachusetts at Amherst Routing Engine Design for the Cognitive Packet Networks Taskin Kocak and Jude Seeber University of Central Florida 3:00-3:30 - Break 3:30-4:30 - Invited Talk Ravinder Sabhikhi, IBM Network processor requirements for processing higher layer protocols such as TCP/IP 4:30-5:00 - Break 5:00-6:00 - Session 2: Analysis and Scheduling Worst-Case Execution Time Estimation for Hardware-assisted Multithreaded Processors Patrick Crowley and Jean-Loup Baer University of Washington Multiprocessor Scheduling in Processor-based Router Platforms: Issues and Ideas Anand Srinivasan, Philip Holman, James Anderson, Sanjoy Baruah and Jasleen Kaur University of North Carolina at Chapel Hill SUNDAY, FEBRUARY 9 ****************** 8:55-9:00 - Welcome 9:00-10:00 - Keynote Address Jonathan Turner, Washington University in St. Louis 10:00-10:30- Break 10:30-12:00- Session 3: Hardware 2 The FlowStorm Multithreaded Packet Processor Steve Melvin, Mario Nemirovsky, Enric Musoll, Jeff Huynh, Rodolfo Milito, Hector Urdaneta, and Koroush Saraf Exploring trade-offs in performance and programmability of processing element topologies for network processors Matthias Gries, Chidamber Kulkarni, Christian Sauer, and Kurt Keutzer University of California, Berkeley, Infineon Technologies Packet Classification and Termination in a Protocol Processor Ulf Nordqvist and Dake Liu Linkęping University, Sweden 12:00-1:30 - Lunch 1:30-3:00 - Session 4: Software and Modeling A Programming Model for Network Processors Niraj Shah, William Plishker and Kurt Keutzer University of California, Berkeley NEPAL: A Framework for Efficiently Structuring Applications for Network Processors Gokhan Memik and William H. Mangione-Smith University of California, Los Angeles Efficient and Faithful Performance Modeling for Network Processor-Based System Designs Prashant Pradhan, Wen Xu, Indira Nair and Sambit Sahu IBM T.J. Watson Research Center, Princeton University 3:00-3:30 - Break 3:30-4:30 - Session 5: Filtering and Classification High-speed Legitimacy-based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200 Roshan Thomas, Brian Mark, Tommy Johnson and James Croall Network Associates Laboratories, George Mason University Directions in Packet Classification for Network Processors Michael E. Kounavis, Alok Kumar, Harrick Vin, Raj Yavatkar and Andrew T. Campbell Columbia University, University of Texas at Austin, Intel Corp. 4:30-4:50 - Break 4:50-6:15 - Panel Session Network Processors: Challenges and Implications Moderator: Mark Franklin, Washington University in St. Louis Panelists: Prashant Chandra, Intel Marco Heddes, Transwitch John Marshall, Cisco Michael Miller, IDT Keith Morris, AMCC Ravinder Sabhikhi, IBM PROGRAM COMMITTEE Anant Agarwal, MIT Andrew Campbell, Columbia University Patrick Crowley, University of Washington Mark Franklin, Washington University in St. Louis Haldun Hadimioglu, Polytechnic University Kenneth Mackenzie, Georgia Tech Bill Mangione-Smith, UCLA John Marshall, Cisco Systems Daniel Mlynek, EPFL (Switzerland) Mohammad Peyravian, IBM Corporation Dimitrios Stiliadis, Bell Labs Jonathan Turner, Washington University in St. Louis Mateo Valero, UPC (Spain) Tilman Wolf, University of Massachusetts Peter Z. Onufryk, IDT Raj Yavatkar, Intel Corporation ORGANIZERS Patrick Crowley, University of Washington (pcrowley@cs.washington.edu) Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu) Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu) Peter Z. Onufryk, IDT (peter.onufryk@idt.com) University of North Carolina at Chapel Hill _____________________________________________________________________ To be removed from the npw-announce list, send mail to npw-announce-admin@cs.washington.edu (or reply to this message) with both "REMOVE" in the subject line and the email address to be removed in the message body.